[All remote jobs](https://jobicy.com/jobs.md)[![Deepgram logo](https://jobicy.com/data/server-nyc0409/galaxy/mercury/2020/12/WRILS-201212160008-406229.jpg)](https://jobicy.com/company/deepgram.md)[Deepgram](https://jobicy.com/company/deepgram.md)

# Applied ML Engineer – Edge Devices

AI Summary Deepgram is seeking a senior-to-staff Applied ML Engineer to deploy speech models efficiently on edge devices and non-NVIDIA accelerators. The role focuses on adapting model graphs, operators, precision, and architecture to target runtimes while preserving accuracy, latency, throughput, and memory performance. The engineer will build repeatable conversion, packaging, versioning, and deployment pipelines and collaborate closely with embedded AI engineers and hardware-platform vendors. This is a production-oriented edge ML role rather than research or cloud-serving work, requiring proven deployment experience on real non-GPU hardware.[Apply for this job](#job-application)[View company](https://jobicy.com/company/deepgram.md)ShareRemote from[USA](https://jobicy.com/job-region/usa.md)SalaryUSD 155k–245k / yrDepartment[Software Engineering](https://jobicy.com/categories/engineering.md)EmploymentFull TimeExperienceSeniorPublished7 Nov 2026Apply before7 Dec 2026Listing views55Application actions3Application toolkit

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Opportunity details

## About this role.

### Company Overview

[Deepgram](https://jobicy.com/company/deepgram.md) is the leading platform underpinning the emerging trillion-dollar Voice AI economy, providing real-time APIs for speech-to-text (STT), text-to-speech (TTS), and building production-grade voice agents at scale. More than 200,000 developers and 1,300+ organizations build voice offerings that are ‘Powered by Deepgram’, including Twilio, Cloudflare, Sierra, Decagon, Vapi, Daily, Cresta, Granola, and Jack in the Box. Deepgram’s voice-native foundation models are accessed through cloud APIs or as self-hosted and on-premises software, with unmatched accuracy, low latency, and cost efficiency. Backed by a recent Series C led by leading global investors and strategic partners, Deepgram has processed over 50,000 years of audio and transcribed more than 1 trillion words. There is no organization in the world that understands voice better than Deepgram.

### Company Operating Rhythm

At Deepgram, we expect an AI-first mindset—AI use and comfort aren’t optional, they’re core to how we operate, innovate, and measure performance.

Every team member who works at Deepgram is expected to actively use and experiment with advanced AI tools, and even build your own into your everyday work. We measure how effectively AI is applied to deliver results, and consistent, creative use of the latest AI capabilities is key to success here. Candidates should be comfortable adopting new models and modes quickly, integrating AI into their workflows, and continuously pushing the boundaries of what these technologies can do.

Additionally, we move at the pace of AI. Change is rapid, and you can expect your day-to-day work to evolve just as quickly. This may not be the right role if you’re not excited to experiment, adapt, think on your feet, and learn constantly, or if you’re seeking something highly prescriptive with a traditional 9-to-5.

### About the role

Deepgram’s speech models are among the fastest and most accurate in the world, and today we run them at scale on NVIDIA GPUs. Our customers increasingly need those same models on hardware we don’t control: non-NVIDIA accelerators, edge servers, and embedded platforms with their own inference runtimes, operator sets, and constraints. Getting Deepgram models onto those platforms, with as few changes to the model as possible and no changes to the hardware paradigm, is the job.

As an Applied ML Engineer on the Partner Platform Engineering team, you sit one layer above the metal. You take a Deepgram model as it exists today and adapt it to run correctly and efficiently within a target platform’s existing kernel and runtime paradigm: swapping or reshaping operators, adjusting architecture parameters, choosing quantization and precision schemes, and validating accuracy and latency on the real device. Where a standard kernel isn’t enough, you work with our Embedded AI Engineers, who write the custom kernels, and fit the model to what they build. You also own the deployment process that gets those adapted models onto edge targets repeatably.

This is not a research role and not a cloud-serving role. It is applied ML for edge deployment. It is a great fit for a senior engineer who has already shipped models to non-GPU or edge hardware and wants to do it across many platforms, or a staff-level engineer who wants to define how Deepgram ports speech models to new hardware. We’ll set the level to your experience.

### What you’ll do

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Port Deepgram speech models to non-NVIDIA and edge platforms, adapting model structure and parameters so they run within the target’s existing operator set, runtime, and kernels with minimal modification.

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Own serving-side model decisions for edge targets: quantization and precision choices, operator substitution, graph rewrites, and architecture tweaks that fit a model to a device’s constraints while holding accuracy and latency.

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Validate every port on real hardware: build accuracy, latency, throughput, and memory benchmarks per platform, and catch regressions before a customer does.

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Build the deployment path for edge targets: model packaging, conversion pipelines, versioning, and automated delivery so shipping a model to a new device is repeatable rather than bespoke.

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Work with Embedded AI Engineers when a standard kernel isn’t enough: specify what the model needs, then adapt the model to use the custom kernel they deliver.

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Partner with platform and silicon vendors on their runtimes and toolchains, and turn their expected model format and operator conventions into a working Deepgram deployment.

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Feed edge constraints back to Research and Impeller so future models are easier to port, without taking on research or core productionization work yourself.

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As the team grows, take on adjacent production concerns at the edge: automated deployment, model security and integrity on customer hardware, and fleet-level observability.

### You’ll love this role if you

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Have already fought to get a model running on hardware that wasn’t built for it, and want to do that across many platforms.

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Prefer changing the model to fit the hardware over changing the hardware to fit the model, and know when each is the right call.

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Care about the numbers on the device, not the numbers in the notebook.

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Like being the bridge between the team writing kernels and the team training models.

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Want to ship to customers, not publish.

### It’s important to us that you have

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Hands-on experience deploying ML models to edge or non-NVIDIA hardware in production. This is required. Cloud-only or GPU-only serving experience does not qualify on its own.

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Working knowledge of quantization and precision tradeoffs (INT8, FP16, mixed precision, calibration) and how they affect accuracy and latency on real targets.

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Experience with at least one edge or vendor inference runtime and its conversion toolchain (for example ONNX Runtime, TFLite, ExecuTorch, OpenVINO, Qualcomm AI Engine, or a vendor NPU SDK).

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Ability to modify a model to fit a platform: reading and rewriting model graphs, swapping unsupported operators, and adjusting architecture parameters without breaking accuracy.

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Strong Python and PyTorch, and production-quality engineering habits: tests, reproducibility, and benchmarks that others can rerun.

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Comfort building automation around model conversion and deployment.

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A builder mindset and clear communication: you can scope a port on an unfamiliar platform and drive it to a measured result.

### It would be great if you had

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Experience with speech, audio, or streaming/real-time models specifically.

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Exposure to writing or reading low-level kernels (CUDA, Metal, NEON, or vendor DSP code), enough to collaborate closely with embedded engineers.

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Experience with model security or integrity on deployed devices: signing, encrypted model storage, safe updates.

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Familiarity with several accelerator families (Qualcomm, Apple, ARM, Intel, AMD, or custom NPUs) and their quirks.

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A track record of building internal tooling that made porting or deploying models measurably faster.

Notice: We’re aware of individuals impersonating Deepgram recruiters. All legitimate Deepgram recruiting communication comes from an @[deepgram.com](http://deepgram.com) email address. If you’ve received a message claiming to be Deepgram, please forward it to careers@deepgram.com.

Show more

[Apply now >](https://jobicy.com/jobs/159493-applied-ml-engineer-edge-devices.md)

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![Upload CV](data:image/svg+xml;base64,PHN2ZyB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciIHdpZHRoPSI2NSIgaGVpZ2h0PSI2NSIgZmlsbD0ibm9uZSIgeG1sbnM6dj0iaHR0cHM6Ly92ZWN0YS5pby9uYW5vIj48ZyBjbGlwLXBhdGg9InVybCgjQSkiPjxwYXRoIGQ9Ik0wIDBINjVWNjVIMFYwWiIgZmlsbD0iIzAyOWFlYiIvPjxnIGZpbGw9IiNmZmYiIHN0cm9rZT0iI2ZmZiIgc3Ryb2tlLXdpZHRoPSIyIj48cGF0aCBkPSJNMzMuMDQ5IDE1LjQ1NGExLjQzIDEuNDMgMCAwIDAtMi4wOTcgMGwtNy41NzkgOC4xNDdhMS4zOCAxLjM4IDAgMCAwIC4wOSAxLjk3MyAxLjQ0IDEuNDQgMCAwIDAgMi4wMDgtLjA4OGw1LjEwOS01LjQ5MnYyMC42MWExLjQxIDEuNDEgMCAwIDAgMS40MjEgMS4zOTdjLjc4NSAwIDEuNDIxLS42MjUgMS40MjEtMS4zOTd2LTIwLjYxbDUuMTA5IDUuNDkyYTEuNDQgMS40NCAwIDAgMCAyLjAwOC4wODggMS4zOCAxLjM4IDAgMCAwIC4wOS0xLjk3M2wtNy41NzktOC4xNDZ6TTE2Ljc2OSAzOC40YzAtLjc3My0uNjItMS40LTEuMzg1LTEuNFMxNCAzNy42MjcgMTQgMzguNHYuMTAybC4yMTUgNi4yMjljLjIyMyAxLjY4LjcwMSAzLjA5NSAxLjgxMyA0LjIxOHMyLjUxIDEuNjA3IDQuMTcyIDEuODMzYzEuNi4yMTggMy42MzYuMjE4IDYuMTYuMjE4aDExLjI4bDYuMTYtLjIxOGMxLjY2Mi0uMjI2IDMuMDYxLS43MDkgNC4xNzItMS44MzNzMS41ODktMi41MzggMS44MTMtNC4yMThDNTAgNDMuMTEzIDUwIDQxLjA1NSA1MCAzOC41MDNWMzguNGMwLS43NzMtLjYyLTEuNC0xLjM4NS0xLjRzLTEuMzg1LjYyNy0xLjM4NSAxLjRsLS4xOSA1Ljk1OGMtLjE4MiAxLjM3LS41MTUgMi4wOTUtMS4wMjYgMi42MTJzLTEuMjI4Ljg1My0yLjU4MyAxLjAzOGMtMS4zOTUuMTktMy4yNDMuMTkzLTUuODkzLjE5M0gyNi40NjJjLTIuNjUgMC00LjQ5OC0uMDAzLTUuODkzLS4xOTMtMS4zNTUtLjE4NC0yLjA3Mi0uNTIxLTIuNTgzLTEuMDM4cy0uODQ0LTEuMjQyLTEuMDI2LTIuNjEyYy0uMTg3LTEuNDEtLjE5MS0zLjI3OS0uMTkxLTUuOTU4eiIvPjwvZz48L2c+PGRlZnM+PGNsaXBQYXRoIGlkPSJBIj48cGF0aCBmaWxsPSIjZmZmIiBkPSJNMCAwaDY1djY1SDB6Ii8+PC9jbGlwUGF0aD48L2RlZnM+PC9zdmc+)

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## Role DNA

A quick view of the complexity, pace, ownership and collaboration implied by the job description.

### Job Complexity

5/5EasyHard

### Pace & Pressure

5/5RelaxedFast-paced

### Autonomy Level

5/5GuidedFull ownership

### Communication Load

4/5IndependentCollaborative

AI insightРоль требует редкого практического опыта переноса ML-моделей на разнообразные edge-ускорители, включая квантование, переписывание графов и измерения на реальном оборудовании. Высокая самостоятельность необходима для работы с новыми SDK, ограничениями платформ и внешними вендорами.

## Salary analysis

Estimated compensation compared with the broader US market for similar roles.

Estimated job median (per year)Market rate$200,000US market range (per year)$170k–$260k0$286k

AI insightРаботодатель указывает годовой базовый диапазон $155,000–$245,000 USD; его медиана составляет $200,000 в год. Оценочный рыночный диапазон для senior/staff инженера по edge ML в США составляет $170,000–$260,000 в год и зависит от опыта работы с аппаратными ускорителями, ML-компиляторами и production deployment.

## Core skills

Skills and capabilities most closely associated with this opportunity.

[Edge ML deployment](https://jobicy.com/jobs?search_keywords=Edge%20ML%20deployment.md)[Model quantization](https://jobicy.com/jobs?search_keywords=Model%20quantization.md)[PyTorch](https://jobicy.com/jobs?search_keywords=PyTorch.md)[Python](https://jobicy.com/jobs?search_keywords=Python.md)[ONNX Runtime](https://jobicy.com/jobs?search_keywords=ONNX%20Runtime.md)[TensorFlow Lite](https://jobicy.com/jobs?search_keywords=TensorFlow%20Lite.md)[Model graph rewriting](https://jobicy.com/jobs?search_keywords=Model%20graph%20rewriting.md)[Inference optimization](https://jobicy.com/jobs?search_keywords=Inference%20optimization.md)[Latency benchmarking](https://jobicy.com/jobs?search_keywords=Latency%20benchmarking.md)[Embedded AI](https://jobicy.com/jobs?search_keywords=Embedded%20AI.md)[Model conversion pipelines](https://jobicy.com/jobs?search_keywords=Model%20conversion%20pipelines.md)[NPU SDKs](https://jobicy.com/jobs?search_keywords=NPU%20SDKs.md)[Automated deployment](https://jobicy.com/jobs?search_keywords=Automated%20deployment.md)[Speech models](https://jobicy.com/jobs?search_keywords=Speech%20models.md)[Performance profiling](https://jobicy.com/jobs?search_keywords=Performance%20profiling.md)

Sample interview questionsDescribe a production ML model port you completed for edge or non-GPU hardware. What constraints did you encounter?I would explain the source model and target runtime, then describe unsupported operators, memory limits, precision constraints, and latency targets. I would quantify the final accuracy, latency, throughput, and memory results and explain how I made the conversion reproducible.

How do you choose between INT8, FP16, and mixed-precision inference for an edge deployment?

I begin with the target accelerator’s supported kernels and benchmark constraints, then establish an accuracy baseline. I test calibrated INT8 and mixed precision where sensitive layers require higher precision, comparing quality, latency, memory use, and operational stability before selecting a deployment configuration.

What is your approach when a target inference runtime does not support a required model operator?

I first determine whether the operator can be decomposed into supported primitives or safely rewritten in the model graph. If a custom kernel is necessary, I define its expected inputs, outputs, numerical behavior, and performance requirements, then validate the integrated model against the original baseline.

How would you build a repeatable deployment pipeline for models targeting several accelerator families?

I would version model artifacts, conversion settings, runtime versions, calibration data, and benchmark results. The pipeline would automate export, graph transformations, compilation or packaging, device validation, regression gates, signing where needed, and delivery of traceable release artifacts.

How do you balance model accuracy against latency and memory limits on a real device?

I define measurable acceptance thresholds for accuracy, tail latency, throughput, and memory before optimization. I then use profiling to prioritize the highest-cost operations and iteratively test changes such as quantization, operator substitutions, architecture adjustments, and batching behavior on the actual target hardware.

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