I am an Electronic Engineer specializing in digital design, functional verification, embedded systems, PCB bring-up, and control systems. My academic and practical work focuses on building and validating reliable hardware and firmware systems.
I have hands-on experience with SystemVerilog, UVM, SVA, constrained-random verification, self-checking testbenches, coverage-driven verification, and RTL design. I built a complete UVM verification environment for an IEEE-754 floating-point multiplier and achieved 100% functional and code coverage.
I have designed a 32-bit RV32I RISC-V Harvard architecture core, memory-mapped peripherals, and FPGA applications. My work includes post-synthesis and post-implementation timing simulations, SoC integration, and assembly-level software development.
I also work across embedded software and hardware development, including C, C++, Python, embedded Linux, FreeRTOS, Zephyr, device drivers, and common communication interfaces such as SPI, I2C, and UART. I have designed PCB subsystems and performed board-level connectivity, reset, clock, and power-rail validation.
In control engineering, I have developed and validated real-time state-space control algorithms using MATLAB/Simulink and C. I am comfortable with system identification, LQR, pole placement, and experimental performance analysis.
I am a native Spanish speaker with advanced English proficiency and elementary French. I am interested in opportunities involving ASIC/SoC verification, digital design, embedded systems, FPGA development, and hardware validation.