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Embedded AI Engineer, On-Device Models

AI Summary
Deepgram is hiring a senior-to-staff Embedded AI Engineer to make speech models performant on constrained edge hardware. The role focuses on custom kernels, low-level runtime components, quantization, operator fusion, and architecture-specific optimization for SoCs, NPUs, DSPs, and embedded targets. The engineer will benchmark latency, accuracy, memory, power, and thermals while extending vendor toolchains where standard operators are insufficient. Success requires close collaboration with applied ML teams and silicon vendors, plus the ability to independently turn ambiguous hardware constraints into reusable production components. This is a highly specialized, rapidly evolving role in on-device speech AI.
Remote from
USA
Salary
USD 219,300–274,100 / yr
Employment
Full Time
Experience
Senior
Published
Apply before
7 Dec 2026
Listing views
40
Application actions
3
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Opportunity details

About this role.

Company Overview

Deepgram is the leading platform underpinning the emerging trillion-dollar Voice AI economy, providing real-time APIs for speech-to-text (STT), text-to-speech (TTS), and building production-grade voice agents at scale. More than 200,000 developers and 1,300+ organizations build voice offerings that are ‘Powered by Deepgram’, including Twilio, Cloudflare, Sierra, Decagon, Vapi, Daily, Cresta, Granola, and Jack in the Box. Deepgram’s voice-native foundation models are accessed through cloud APIs or as self-hosted and on-premises software, with unmatched accuracy, low latency, and cost efficiency. Backed by a recent Series C led by leading global investors and strategic partners, Deepgram has processed over 50,000 years of audio and transcribed more than 1 trillion words. There is no organization in the world that understands voice better than Deepgram.

Company Operating Rhythm

At Deepgram, we expect an AI-first mindset—AI use and comfort aren’t optional, they’re core to how we operate, innovate, and measure performance.

Every team member who works at Deepgram is expected to actively use and experiment with advanced AI tools, and even build your own into your everyday work. We measure how effectively AI is applied to deliver results, and consistent, creative use of the latest AI capabilities is key to success here. Candidates should be comfortable adopting new models and modes quickly, integrating AI into their workflows, and continuously pushing the boundaries of what these technologies can do.

Additionally, we move at the pace of AI. Change is rapid, and you can expect your day-to-day work to evolve just as quickly. This may not be the right role if you’re not excited to experiment, adapt, think on your feet, and learn constantly, or if you’re seeking something highly prescriptive with a traditional 9-to-5.

About the Role

Deepgram’s speech models are among the fastest and most accurate in the world, and we have deep machinery for running them on NVIDIA GPUs. Our customers need them on everything else: non-NVIDIA accelerators, embedded SoCs, mobile application processors, DSPs and NPUs, and purpose-built devices with tight memory, compute, thermal, and power budgets. When a target platform’s standard kernels and runtime can’t run a Deepgram model well enough, someone has to go below them. That is this role.

As an Embedded AI Engineer on the Partner Platform Engineering team, you work at the lowest layer of our edge stack. You write and optimize custom kernels and operators for specific hardware, collapse models onto device-specific execution units, and do the target-side quantization and assembly-level tuning that standard toolchains can’t. You hand what you build up to Applied ML Engineers, who fit Deepgram models to your kernels. Your work is what makes a new hardware platform viable for Deepgram at all.

This role is a great fit for a senior embedded engineer who has spent their career close to the metal and wants to point that at speech AI, or a staff-level engineer who wants to define how Deepgram’s models get onto new silicon. We’ll set the level to your experience.

What You’ll Do

  • Write and optimize custom kernels and operators (C, C++, Rust, and platform assembly or intrinsics) for non-NVIDIA accelerators, embedded SoCs, DSPs, and NPUs where the vendor’s standard operator set is insufficient for Deepgram models.

  • Own target-side optimization: collapse models onto device execution units through quantization, operator fusion, memory layout, and architecture-specific compilation to meet latency, memory, power, and thermal budgets.

  • Integrate with vendor NPU/DSP toolchains and edge inference runtimes, and extend them with custom operators when the graph doesn’t map cleanly.

  • Deliver kernels and runtime components as reusable building blocks that Applied ML Engineers can target when adapting models, with clear interfaces and documented constraints.

  • Build performance-critical runtime code for embedded environments, including embedded Linux, bare-metal, and RTOS targets.

  • Establish per-platform benchmarking and validation for latency, accuracy, power, memory footprint, and utilization, and catch regressions before they ship.

  • Partner with silicon and platform vendors on SDK integration and low-level performance tuning for new chipsets and reference platforms.

  • Feed hardware constraints back to Applied ML and Research so model designs are easier to land on constrained targets.

You’ll Love This Role If You

  • Find deep satisfaction in making a large model run on hardware that was never meant to run it, and still hitting accuracy and latency targets.

  • Reach for the profiler and the ISA manual before you reach for a bigger chip.

  • Would rather write the kernel than wait for the vendor to ship it.

  • Care about the details that don’t show up in a cloud benchmark: cold start, power draw, thermals, memory fragmentation, cache behavior.

  • Prefer hard, constrained, ship-it problems over open-ended research.

  • Care about the details that don’t show up in a cloud benchmark: cold-start time, power draw, thermals, and memory fragmentation.

It’s Important To Us That You Have

  • Experience delivering production systems on resource-constrained hardware — embedded systems, mobile, edge AI, or small low-power devices.

  • Strong proficiency in C, C++, and/or Rust, with experience writing performance-critical code for constrained environments.

  • Hands-on experience with model optimization for on-device deployment, including quantization, pruning, knowledge distillation, or architecture-specific compilation.

  • Familiarity with edge inference runtimes (e.g., ONNX Runtime, TensorRT, TFLite, ExecuTorch) and/or vendor-specific NPU/DSP toolchains.

  • A strong understanding of hardware-software interaction — CPU/GPU/NPU/DSP architectures, memory hierarchies, fixed-point/integer arithmetic, and power management — and how they affect inference performance.

  • Experience working close to the metal: bare-metal or RTOS environments (e.g., FreeRTOS, Zephyr), embedded Linux, or microcontroller and edge SoC development.

  • Strong communication skills and a builder mindset — you can scope an ambiguous optimization problem, drive it to a measurable result, and explain the tradeoffs clearly.

It Would Be Great if You Had

  • Experience with real-time audio processing on embedded platforms — DSP pipelines, audio codec optimization, wake-word or always-on listening, or streaming inference on microcontrollers and edge SoCs.

  • Depth in ML optimization techniques — custom quantization schemes, mixed-precision inference, or neural architecture search for edge targets.

  • Background in hardware evaluation and benchmarking — systematically comparing accelerators, SoCs, or GPUs for specific workload profiles.

  • Experience shipping AI features in consumer products at scale, and the instinct for what “production quality” means on a battery-powered device.

  • Familiarity with model compilation and optimization toolchains and their tradeoffs across hardware targets.

  • Experience with secure, robust on-device deployment practices — code signing, encrypted model storage, and safe update mechanisms.

Notice: We’re aware of individuals impersonating Deepgram recruiters. All legitimate Deepgram recruiting communication comes from an @deepgram.com email address. If you’ve received a message claiming to be Deepgram, please forward it to careers@deepgram.com.

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This job listing has been manually reviewed by the Jobicy Trust & Safety Team for compliance with our posting guidelines, including verification of the company's legitimacy, accuracy of job details, clarity of remote work policy, and absence of misleading or fraudulent content.

Role DNA

A quick view of the complexity, pace, ownership and collaboration implied by the job description.

Job Complexity

5/5
EasyHard

Pace & Pressure

5/5
RelaxedFast-paced

Autonomy Level

5/5
GuidedFull ownership

Communication Load

4/5
IndependentCollaborative
AI insightThe position requires deep expertise across embedded programming, hardware architecture, compiler/runtime optimization, and on-device ML inference. Engineers must solve novel performance problems under strict latency, memory, thermal, and power constraints.

Salary analysis

Estimated compensation compared with the broader US market for similar roles.

Estimated job median (per year)Market rate
$246,700
US market range (per year)$210k–$290k
AI insightThe employer discloses a yearly base-pay range of $219,300–$274,100 USD, with a midpoint of $246,700. This is a credible range for a senior or staff-level embedded AI engineering role in the US; the estimated US market range is $210,000–$290,000 per year.

Core skills

Skills and capabilities most closely associated with this opportunity.

Sample interview questions
Describe a time you optimized an ML workload for a device with tight latency, memory, or power constraints.

I begin by establishing a measured baseline using device-side profiling, then identify the dominant bottleneck in compute, memory bandwidth, scheduling, or data movement. I apply targeted changes such as quantization, operator fusion, layout changes, or platform-specific kernels, and validate accuracy alongside latency, memory, and power metrics.

How would you approach implementing a custom operator when an NPU runtime does not efficiently support part of a speech model?

I would first verify that graph rewriting or supported operator decompositions cannot meet the target metrics. Then I would define a stable operator interface, implement and tune the hardware-specific kernel, integrate it with the runtime’s execution and memory model, and benchmark it across representative inputs and device conditions.

What factors do you consider when selecting an integer or mixed-precision quantization strategy?

I consider operator sensitivity, activation distributions, available hardware data paths, calibration quality, memory constraints, and end-to-end accuracy requirements. I validate per-layer error and production workload quality, using mixed precision for sensitive operations when uniform low-bit quantization produces unacceptable degradation.

How do you prevent performance regressions across multiple embedded hardware targets?

I create repeatable per-platform benchmark suites with fixed model versions, representative audio inputs, and thresholds for latency, memory, accuracy, power, and cold-start behavior. Results should run in CI or a controlled hardware lab, with regressions attributed to model, compiler, runtime, or kernel changes before release.

How would you communicate a hardware limitation to an Applied ML team?

I would provide measurable constraints, such as unsupported operations, memory-bandwidth limits, or latency budgets, along with profiling evidence. I would propose practical alternatives—such as operator substitutions, fusion opportunities, quantization constraints, or architecture changes—and explain their expected quality and performance tradeoffs.

This analysis is generated from the job description. Salary estimates, role characteristics and sample answers are guidance, not employer-provided facts.
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